Compiler Engineer

Role Overview

We are seeking a highly skilled Compiler Engineer to join our AI Enablement team. In this role, you will lead the transition from traditional architectures toward next-generation RISC-V-based AI accelerators. You will be at the forefront of hardware-software co-design, leveraging the MLIR (Multi-Level Intermediate Representation) framework and the IREE (Intermediate Representation Execution Environment) ecosystem to optimize on-device AI workloads for edge computing.

Your primary focus will be developing high-performance compiler pipelines that bridge high-level AI frameworks with custom RISC-V hardware, specifically targeting Transformer attention acceleration and power-efficient inference for automotive and IoT applications.

Key Responsibilities

• MLIR Development: Define new dialects, lowering passes, and transformations within the MLIR framework to optimize high-level models (e.g., PyTorch, TensorFlow) for specialized hardware targets.
• HW/SW Co-Design: Collaborate closely with RTL design, verification, and computer architecture teams to simultaneously evolve the compiler and the underlying RISC-V hardware.
• Performance Engineering: Develop custom compiler passes to maximize AI inference speed, focusing on critical bottlenecks like Transformer attention mechanisms.
• Workload Modeling: Utilize advanced architectural exploration tools to model AI workloads and identify hardware-software bottlenecks during the pre-silicon phase.
• Low-Level Code Gen: Implement optimized code generation for 1D/2D register architectures and manage explicit cache/memory hierarchies for maximum data throughput.

Technical Requirements

• MLIR Expertise: Proven experience in building and maintaining MLIR-based pipelines, including dialect definition and progressive lowering.
• RISC-V ISA Knowledge: Deep understanding of the RISC-V Instruction Set Architecture, with experience in ISA customization or optimizing custom hardware extensions.
• IREE Ecosystem: Hands-on experience with the IREE project for compiling and deploying machine learning models on edge devices.
• Programming Languages: Strong proficiency in C++ for backend compiler development and Python for frontend prototyping and tooling.
• Architecture Proficiency: Solid understanding of computer architecture, specifically hardware acceleration for AI/ML and memory management strategies.

Preferred Qualifications

• Experience with performance modeling tools (e.g., cycle-accurate simulators or workload explorers).
• Background in developing kernels for specific parallel patterns (Map/Reduce, Prefix Sum) or optimized math libraries.
• Familiarity with the 2026 AI landscape, focusing on low power, "AI at the Edge" applications for automotive or high-performance IoT.

Why Join Us?

This is a unique opportunity to define the future of AI hardware. As we shift our focus toward RISC-V-based acceleration, you will have a direct impact on the architecture and software stack used by millions of devices in the automotive and edge computing sectors. We offer a collaborative environment where compiler innovation and hardware design happen in lockstep.